1. Field of the Invention
The present invention relates to an electroplating apparatus and an electroplating method, and more particularly to an electroplating apparatus and an electroplating method useful for filling fine interconnect pattern formed in a surface of a substrate (surface to be plated), such as a semiconductor wafer, with a metal, such as copper, to form embedded interconnects.
2. Description of the Related Art
In recent years, instead of using aluminum or aluminum alloys as a material for forming circuits on a semiconductor substrate, there is an eminent movement towards using copper (Cu) which has a low electric resistivity and high electromigration resistance. Copper interconnects are generally formed by filling copper into fine interconnect recesses formed in a surface of a substrate. There are known various techniques for forming such copper interconnects, including chemical vapor deposition (CVD), sputtering, and plating. According to any such technique, a copper film is formed in a substantially entire surface of a substrate, followed by removal of unnecessary copper by chemical mechanical polishing (CMP).
FIGS. 28A through 28C illustrate, in a sequence of process steps, an example of forming such a substrate W having copper interconnects. First, as shown in FIG. 28A, an insulating film (interlevel dielectric film) 2 of SiO2 or low-k material is deposited on a conductive layer 1a in which semiconductor devices are formed, which is formed on a semiconductor base 1. Contact holes 3 and trenches 4 for interconnect recesses are formed in the insulating film 2 by the lithography/etching technique. Thereafter, a barrier layer 5 of TaN, TiN or the like is formed on the surface, and a seed layer 7 as an electric supply layer for electroplating is formed on the barrier layer 5.
Then, as shown in FIG. 28B, copper plating is performed onto the surface of the substrate W to fill the contact holes 3 and the trenches 4 with copper and, at the same time, deposit a copper film 6 on the insulating film 2. Thereafter, the copper film 6, the seed layer 7 and the barrier layer 5 on the insulating film 2 are removed by chemical mechanical polishing (CMP) so as to make the surface of the copper film 6 filled in the contact holes 3 and the trenches 4 for interconnects and the surface of the insulating film 2 lie substantially on the same plane. Interconnects composed of the copper film 6 are thus formed in the insulating film 2, as shown in FIG. 28C.
When carrying out electroplating of a surface of a substrate, as shown in FIG. 29, a cathode contact 200 brings into contact with a peripheral region of an conductive layer, such as a seed layer 7, formed on a surface of a substrate W, and a plating solution 204 is filled into between the substrate W and an anode 202 disposed opposite the substrate W. A plated film is deposited on the conductive layer of the substrate W by passing a plating current between the cathode contact 200 and the anode 202 from a power source 206.
Semiconductor wafers and liquid crystal substrates for LSI's tend to increase in area year by year. In line with this tendency, the substrates are posing problems. In detail, as the area of the substrate W increases, the electric resistance (sheet resistance) of the conductive layer, such as a seed layer 7, ranging from the cathode contact 200 on the periphery of the substrate W to the center of the substrate W also increases. As a result, a potential difference produces in-plane of the substrate W, causing a difference in the plating rate. FIG. 29 is an electrical equivalent circuit diagram of general electroplating, and the following resistance components exist in this circuit:
R1: Power source wire resistance between power source 206 and anode 202, and various contact resistances
R2: Polarization resistance at anode 202
R3: Resistance of plating solution 204
R4: Polarization resistance at cathode contact
R5: Resistance of conductive layer (sheet resistance)
R6: Power source wire resistance between cathode contact and power source 206, and various contact resistances
As can be seen from FIG. 29, when the resistance R5 of the conductive layer becomes higher than the other electric resistances R1 to R4 and R6, the potential difference arising between both ends of this resistance R5 of the conductive layer increases, and accordingly, a difference occurs in the plating current. Thus, the plated film growth rate lowers at a position distant from the cathode contact 200. If a film thickness of the conductive layer is small, the resistance R5 further increases, and this phenomenon appears conspicuously. This phenomenon, called terminal effect, means that the current density differs in-plane of the substrate W, and the characteristics of a plated film itself (resistivity, purity, burial characteristics, etc. of the plated film) are not uniform in-plane.
As a method for avoiding these problems, it is conceivable to increase the thickness of the conductive layer or decrease the electric conductivity of the conductive layer. However, the substrate is subject to various restrictions even in manufacturing steps other than plating. For example, when a thick conductive layer is formed on a fine pattern by sputtering, voids easily occur inside the pattern. Thus, it is impossible to easily increase the thickness of the conductive layer or change the film type of the conductive layer.
In order to solve above problem, the applicant has proposed a plating apparatus wherein a high resistance structure 208, which has lower electric resistivity than the electric resistivity of the plating solution, is disposed between an anode 202 and a substrate W, as shown in FIG. 30. With this structure, an electric equivalent circuit diagram is shown in FIG. 30, and a resistance Rp of the high resistance structure 208 is added as compared to the electric equivalent circuit diagram shown in FIG. 29. Therefore, if a value of the resistance Rp of the high resistance structure 208 becomes high, a value ((R2+R3+Rp+R4)/(R2+R3+Rp+R4+R5)) comes near one, the influence of the resistance R5, i.e., a resistant factor (sheet resistance) of the conductive layer becomes low.
A copper seed layer, formed by, e.g., sputtering, CVD, ALD or electroless plating, is generally used as the seed layer 7; and such a copper seed layer is becoming thinner year by year with the progress toward finer interconnects. For example, a thickness of a copper seed layer in the field region of a substrate is around 600 angstrom in the manufacturing of a 65 nm-generation semiconductor device. A thickness of a copper seed layer is expected to be not more than 500 angstrom in a 45 nm-generation. In the next generation and the following generation, it is expected that a thickness of a copper seed layer will be not more than 300 angstrom, or that copper will be plated directly on a surface of a barrier layer of, e.g., ruthenium without forming a copper seed layer.
The electric resistance (sheet resistance) of a current copper seed layer having the above thickness is not more than 1 Ω/sq. The terminal effect, which depends on the sheet resistance of such a seed layer, can be reduced by interposing a resistor body between a substrate, which is connected to a cathode contact and serves as a cathode, and an anode, or by decreasing the acid concentration of a plating solution so as to increase the resistance of the plating solution itself. This can prevent a copper plated film from becoming thinner in the central portion of the substrate than in the peripheral portion, enabling the formation of a copper film having a uniform thickness on the surface of the substrate.
The applicant has proposed the use of divided anodes in any desired shape or the use of an insoluble anode (see Japanese Patent Laid-Open Publication Nos. 2002-129383 and 2005-213610). The applicant has also proposed to apply a voltage between an anode and a surface (conductive layer) of a substrate when placing the substrate into a plating bath, the voltage being such as to provide an average cathode current density of 1 to 30 mA/cm2 for the surface (conductive layer) of the substrate (see Japanese Patent Laid-Open Publication No. 2004-218080). It has also been proposed to control a thickness of a plated film by electrical control using a switching mechanism that includes a number of power sources or resistances.